Researchers Develop Innovative Algorithm for Circuit Power Analysis

In a significant advancement for the field of electronic design automation, a team of researchers from Zhejiang University and Shanghai Hexin Industrial Software Co., Ltd. has unveiled a novel algorithm aimed at generating pseudo-datasets for integrated circuit (IC) power analysis. The study, titled “Algorithm and evaluation of generating pseudo-datasets for integrated circuit power analysis,” addresses the increasing demand for extensive datasets necessary for data-driven machine learning (ML) applications in the design of large-scale digital ICs.

The current standard datasets available in the IC industry often fall short in both quantity and specificity, posing challenges for effective ML implementation. Accessing large-scale industrial or competitive data frequently involves legal restrictions, complicating the data acquisition process. The research team sought to overcome these obstacles by developing a pseudo-circuit generation algorithm based on graph topology.

This innovative approach begins by converting randomly generated directed acyclic graphs (DAGs) into gate-level Verilog pseudo-combinational circuit netlists. This method facilitates the efficient production of a vast number of power analysis examples. Subsequently, the algorithm introduces register units to transform these netlists into pseudo-sequential circuit netlists. By adjusting hyperparameters to control circuit topology and applying suitable sequential constraints during synthesis, the researchers successfully generated a comprehensive pseudo-circuit dataset.

To evaluate the effectiveness of their method, the team utilized mainstream power analysis software to conduct pre-layout average power tests on the circuits generated from their algorithm. The results demonstrated a positive correlation in power consumption distribution trends between the generated pseudo-datasets and established benchmark datasets. The tests were performed using renowned tools, including Synopsys PrimeTime PX and Cadence Voltus.

Significant Findings and Implications

The study’s authors, Zejia LYU, Jizhong SHEN, and Xi CHEN, highlighted the operational efficiency and robustness of the algorithm. They noted that the generated datasets—comprising 1000 sets of combinational and 1000 sets of sequential circuit netlists—exhibited consistent power consumption patterns when tested against benchmark datasets. This consistency underscores the research’s value for future applications in IC design.

Moreover, the algorithm’s capability to generate samples in parallel significantly reduces time overhead, further enhancing its practicality. The researchers also introduced a sequential circuit generation factor, referred to as α, which can be adjusted to manipulate circuit topology and mitigate the zero-value phenomenon often encountered in sequential circuit power analysis.

The implications of this research extend beyond theoretical advancements; they present a practical solution to a pressing issue in the IC industry. By providing a method for generating rich datasets, the study paves the way for improved accuracy in power analysis and supports the integration of machine learning techniques into electronic design processes.

For those interested in the full details of this groundbreaking research, the paper can be accessed at: https://doi.org/10.1631/FITEE.2400677.